The present invention relates to a semiconductor device such as MOSFET and particularly to a semiconductor device having a super junction structure in a drift layer of a vertical MOSFET.
On-resistance of a conventional vertical power MOSFET greatly depends on the electric resistance of its conductive layer (drift layer). Dopant concentration of the drift layer determines the electric resistance of the drift layer. Accordingly, as the dopant concentration becomes higher, the electric resistance can be reduced. The dopant concentration, however, cannot exceed a limit, which depends on the withstand voltage of a pn junction formed between the base layer and the drift layer. Namely, there is a tradeoff between the device withstand voltage and the on-resistance and thus the device withstand voltage or the on-resistance has a limit determined by the device material.
As an example to solve the problem of the tradeoff, a MOSFET with a super junction (SJ) structure formed in the drift layer is known (refer to Japanese Patent Application Laid-Open No. 2001-294461). The SJ structure includes a plurality of n− pillar layers and p− pillar layers formed from a surface of the drift layer toward a depth direction of the device. The n− pillar layers and the p− pillar layers are alternately arranged along the surface of the substrate. In the SJ structure, a non-doped layer is artificially formed by equalizing the amount of charge (amount of impurities) contained in the p-pillar layers with that contained in the n− pillar layers, thus keeping a high withstand voltage in the MOFFET. Further, by equally raising the impurity concentration in the n− pillar layers and in the p-pillar layers, a current flows through the highly doped n− pillar layers, hence a low on-resistance beyond the material limit can be realized.
In the above mentioned MOSFET with the SJ structure formed in the drift layer, the SJ structure area is formed also in the device terminal section and the amount of impurities in the n− pillar layers and in the p− pillar layers should be equally controlled with high precision in order to keep the withstand voltage of the device. However, it is difficult to make the amount of impurities in the n-pillar layers and in the p− pillar layers equal to each other with high precision due to variations in manufacturing and the amount of impurities in the p-pillar layers may get higher than in the n− pillar layers. When actually forming a device, the amount of impurities in the p− pillar layers are made a little higher than that in the n− pillar layers in some cases, in order to assure avalanche capability, or in order to assure the safety operation when the drain-source voltage exceeds the withstand voltage due to an inductive voltage caused by a rapid change in drain-source current due to generation of surge voltage.
When the amount of impurities in the p− pillar layers is higher than that in the n− pillar layers, depletion layers formed near the interface between the n− pillar layers and the p− pillar layers expands from the interface portion to an external portion of the device. The expansion of the depletion layers makes isoelectric lines dense on an outer peripheral surface of the SJ structure area and increases electric field that is a differentiation of potential, thereby decreasing the withstand voltage of the device and deteriorating the device reliability.